71M6534H-DB【PDF 27/132 页】BOARD DEMO 71M6534H

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FDS_6533_6534_004

71M6533/G/H and 71M6534/H Data Sheet

WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are

programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable

communication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated.

Table 16 shows the selectable UART operation modes.

Table 15: Baud Rate Generation

2

* f CKMPU /(64 * (2 - S0REL ))

2

f CKMPU /(32 * (2 - S1REL ))

UART0

UART1

smod

N/A

Using Timer 1

( WDCON[7] = 0)

* f CKMPU / (384 * (256- TH1 ))

Using Internal Baud Rate Generator

( WDCON[7] = 1)

smod 10

10

S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers

( S0RELL, S0RELH, S1RELL, S1RELH ). SMOD is the SMOD bit in the SFR PCON register. TH1 is the high

byte of timer 1.

Table 16: UART Modes

Mode 0

N/A

UART 0

UART 1

Start bit, 8 data bits, parity, stop bit, variable

baud rate (internal baud rate generator)

Mode 1

Mode 2

Mode 3

Start bit, 8 data bits, stop bit, variable

baud rate (internal baud rate generator

or timer 1)

Start bit, 8 data bits, parity, stop bit,

fixed baud rate 1/32 or 1/64 of f CKMPU

Start bit, 8 data bits, parity, stop bit,

variable baud rate (internal baud rate

generator or timer 1)

Start bit, 8 data bits, stop bit, variable baud

rate (internal baud rate generator)

N/A

N/A

1. 8-bit serial modes with parity can be simulated by setting and reading the 9 bit, using the

the slave’s address, it sets the 9 bit to 1, causing a serial port receive interrupt in all the slaves. The

After addressing the slave, the host outputs the rest of the message with the 9 bit set to 0, so no additional

Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with

parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of

8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant

th

control bits TB80 ( S0CON [ 3 ]) and TB81 ( S1CON[3] ) in the S0CON ( SFR 0x98 ) and S1CON ( SFR 0x9B )

SFRs for transmit and RB81 ( S1CON[2] ) for receive operations.

The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals

for inter-processor communication in multi-processor systems. In this case, the slave processors have bit

SM20 ( S0CON[5] ) for UART0, or SM21 ( S1CON[5] for UART1, set to 1. When the master processor outputs

th

slave processors compare the received byte with their address. If there is a match, the addressed slave

will clear SM20 or SM21 and receive the rest of the message. The rest of the slave’s will ignore the message.

th

serial port receive interrupts will be generated.

UART Control Registers:

The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON

and S1CON shown in Table 17 and Table 18, respectively, and the PCON register shown in Table 19 .

Since the TI0 , RI0 , TI1 and RI1 bits are in an SFR bit addressable byte, common practice

would be to clear them with a bit operation, but this must be avoided. The hardware implements

bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after

the read, but before the write, its flag will be cleared unintentionally.

The proper way to clear these flag bits is to write a byte mask consisting of all ones except for

a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore

ones written to them.

Rev 2

27

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